Conventionally, a Si (silicon)-based normally-off FET (Si-FET) is mainly used for a semiconductor device. The normally-off FET is a transistor that is made conductive between the drain and the source when a gate voltage is applied between the gate and the source and made non-conductive between the drain and the source when a gate voltage is not applied between the gate and the source.
On the other hand, the Si-FET has been approaching its limitation in terms of physical performance. Among wide gap semiconductor FETs that are expected to have performance exceeding that of the Si-FET, an HFET (hetero FET) using two-dimensional electron gas, such as a GaN semiconductor FET (also referred to as a GaN-FET) is attracting attention. The GaN-FET is able to relatively easily achieve a high withstand voltage, a high-temperature operation, and a low on-resistance by heterojunction and thus is highly useful. However, the GaN-FET is typically a normally-on FET and is difficult to be used as a normally-off FET.
The normally-on FET is switched on even when a gate voltage is 0 V (volt). A normally-off operation is strongly requested as a power device in terms of safety. Thus, a composite semiconductor device having a cascode configuration in which a normally-on FET and a normally-off FET are connected in series to thereby realize a normally-off semiconductor switch as a whole of the device has been proposed. In the cascode configuration, since a mirror effect is suppressed as widely known, a high-speed operation of the normally-on FET is not impaired.
PTL 1 discloses a composite semiconductor device having a cascode configuration in which a normally-on switching element and a normally-off switching element are connected in series. Voltage clamping means is provided as a protection circuit between the drain (or the collector) and the gate (or the base) of the normally-off switching element.
PTL 2 discloses a composite semiconductor device having a cascode configuration in which a normally-on power semiconductor switching element constituted by a wide gap semiconductor and a plurality of normally-off metal insulating film semiconductor field effect transistors are connected in series. A high-speed diode that is connected in parallel with such cascode elements is provided and a switching loss caused by a reverse recovery current is reduced.
PTL 3 discloses a composite semiconductor device having a cascode configuration in which each of the normally-on GaN semiconductors FET that are manufactured in various configurations and a normally-off FET are connected in series.